Why do I see incorrect audio frequency output from the HDMI Intel® FPGA IP RX core when fixed rate link(FRL) mode is enabled? - Why do I see incorrect audio frequency output from the HDMI Intel® FPGA IP RX core when fixed rate link(FRL) mode is enabled? Description Due to a problem with the HDMI Intel® FPGA IP RX core, audio output is broken when FRL mode is enabled. The internal audio clock is incorrectly recovered from the link clock based on the received number of pixels per clock(N) and CTS values in FRL mode. The audio works correctly in Transition Minimized Differential Signaling(TMDS) mode. Resolution There is no work around for this problem in FRL mode. If possible use TMDS mode. This problem has been fixed in the Intel® Quartus® Prime Pro Edition software versions 20.1. Custom Fields values: ['novalue'] Troubleshooting 1507820295 True ['HDMI IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.1 19.4 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']