Why does the 25G Ethernet Intel® Stratix® 10 FPGA IP with IEEE 1588 and RS-FEC enabled sometimes fail to achieve timestamp accuracy of +/-5 ns? - Why does the 25G Ethernet Intel® Stratix® 10 FPGA IP with IEEE 1588 and RS-FEC enabled sometimes fail to achieve timestamp accuracy of +/-5 ns? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software v21.3 and earlier, you might see the RX timestamps are shifted by 4 clock cycles for packets with SOP asserted near RS-FEC alignment marker. As a result, the generated timestamps will have accuracy error of approximately 10 ns. This problem occurs when both IEEE 1588 and RS-FEC are enabled in the 25G Ethernet Intel® Stratix® 10 FPGA intellectual property (IP). Resolution There is no workaround for this problem in the Intel® Quartus® Prime Pro Edition Software v21.3 and earlier. This problem is fixed starting from the Intel® Quartus® Prime Pro Edition Software v21.4. Custom Fields values: ['novalue'] Errata 15010098636 False ['25G Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.4 21.3 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']