Error (10228): Verilog HDL error at lvds_rx_lvds_rx.v(49): module "lvds_rx_accum" cannot be declared more than once - Error (10228): Verilog HDL error at lvds_rx_lvds_rx.v(49): module "lvds_rx_accum" cannot be declared more than once Description You may see this error in the Quartus® II software versions 13.1 and later when implementing the ALTLVDS_RX IP with external Altera_PLL and Dynamic Phase Alignment (DPA) enabled with more than two channels in Arria® V devices. Resolution To work around this, first, complete the steps for implementing ALTLVDS_RX and ALTLVDS_TX with external PLL mode as described in the related solutions. Then, after running Analysis and Synthesis in the Quartus II software, copy the lvds_rx_lvds_rx module from the contents of the file db/lvds_rx_lvds_rx.v into the lvds_rx.v file. This will add the module lvds_rx_lvds_rx into the lvds_rx.v file. Ensure all occurrences of rx_dpaclock is 8 bits and all connections of rx_dpaclock are correct. For example, .dpaclkin(rx_dpaclock), instead of: .dpaclkin({8{rx_dpaclock}}), Related Articles How do I insert an LVDS buffer between an Altera_PLL and ALTLVDS_RX or ALTLVDS_TX megafunction in external PLL mode for Cyclone V, Arria V, and Stratix V devices? How do I implement and connect between an external Altera_PLL and an ALTLVDS_RX with Dynamic Phase Alignment (DPA) enabled? Custom Fields values: ['novalue'] Troubleshooting 2205865248 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.1 ['Arria® V FPGAs and SoCs', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']