Why are the dedicated HPS I/O output pins for Intel Agilex® 7 SoC FPGA incorrectly assigned in the pinout report (.pin file)? - Why are the dedicated HPS I/O output pins for Intel Agilex® 7 SoC FPGA incorrectly assigned in the pinout report (.pin file)? Description Due to a problem with the fitter inside the Intel® Quartus® Prime Pro Edition Software versions 20.3 to 21.4, the dedicated HPS I/O output pins will be placed in the wrong pin locations. This will be reflected in the pinout report (.pin file) that is generated by the Intel® Quartus® Prime Pro Edition Software during the fitter stage. Resolution Download and install the following patch and readme file to fix this problem for the Intel® Quartus® Prime Pro Edition version 21.4: Windows (.exe) patch 0.47 for Intel Quartus Prime Pro Edition Software version 21.4 Linux (.run) patch 0.47 for Intel Quartus Prime Pro Edition Software version 21.4 Readme for the Intel Quartus Prime Pro Edition Software version 21.4 patch 0.47 (.txt) This issue is fixed starting with the Intel Quartus Prime Pro Edition Software version 22.1. Custom Fields values: ['novalue'] Troubleshooting 18016708340, 14016692819 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.1 20.3 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']