Why can't I simulate the Arria II IP Compiler for PCI Express in Quartus 13.1? - Why can't I simulate the Arria II IP Compiler for PCI Express in Quartus 13.1? Description HardCopy® IV and Stratix® II support was removed from 13.1. You may see an error such as that shown below: # ** Error: (vlog-7) Failed to open design unit file "/tools/acds/13.1/162/linux64/quartus/eda/sim_lib/stratixiigx_hssi_atoms.v" in read mode. In Quartus® II 13.1 you must modify the simulation scripts as detailed below. Resolution The file runtb.do needs to be modified: Replace vlib stratixiigx_hssi_ver vmap stratixiigx_hssi_ver stratixiigx_hssi_ver vlog -work stratixiigx_hssi_ver /eda/sim_lib/stratixiigx_hssi_atoms.v vlog -work stratixiigx_hssi_ver /libraries/megafunctions/alt2gxb.v with vlib stratixiigx_hssi_ver vmap stratixiigx_hssi_ver stratixiigx_hssi_ver vlog -work stratixiigx_hssi_ver stratixiigx_hssi_atoms.v vlog -work stratixiigx_hssi_ver alt2gxb.v Remove or comment out: vlib hardcopyiv_hssi_ver vmap hardcopyiv_hssi_ver hardcopyiv_hssi_ver vmap hardcopyiv_hssi hardcopyiv_hssi_ver vlog -work hardcopyiv_hssi /eda/sim_lib/hardcopyiv_hssi_atoms.v vlib hardcopyiv_pcie_hip_ver vmap hardcopyiv_pcie_hip_ver hardcopyiv_pcie_hip_ver vmap hardcopyiv_pcie_hip hardcopyiv_pcie_hip_ver vlog -work hardcopyiv_pcie_hip /eda/sim_lib/hardcopyiv_pcie_hip_atoms.v Remove or comment out the hardcopyiv references from eval vsim -novopt -t ps -L altera_mf_ver -L lpm_ver -L sgate_ver -L stratixiigx_hssi_ver -L stratixiv_hssi_ver -L stratixiv_pcie_hip_ver -L arriaii_hssi_ver -L arriaii_pcie_hip_ver -L arriaiigz_hssi_ver -L arriaiigz_pcie_hip_ver -L cycloneiv_hssi_ver -L cycloneiv_pcie_hip_ver -L hardcopyiv_hssi_ver -L hardcopyiv_pcie_hip_ver PCIE_JAVA_STR_RPL_TOP_chaining_testbench to eval vsim -novopt -t ps -L altera_mf_ver -L lpm_ver -L sgate_ver -L stratixiigx_hssi_ver -L stratixiv_hssi_ver -L stratixiv_pcie_hip_ver -L arriaii_hssi_ver -L arriaii_pcie_hip_ver -L arriaiigz_hssi_ver -L arriaiigz_pcie_hip_ver -L cycloneiv_hssi_ver -L cycloneiv_pcie_hip_ver -L PCIE_JAVA_STR_RPL_TOP_chaining_testbench where PCIE_JAVA_STR_RPL_TOP_chaining_testbench is the name of your top_chaining_testbench This issue will be fixed in a future version of the Quartus II software. Related Articles Why does the simulation script for the PCIe HIP chaining_dma example design fail? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® II GX FPGA'] ['novalue'] ['novalue'] ['novalue']