Why is my design failing when I instantiated the Configuration Clock IP in the Quartus® Prime Pro Edition Software version 24.3.1? - Why is my design failing when I instantiated the Configuration Clock IP in the Quartus® Prime Pro Edition Software version 24.3.1? Description Due to a problem in the Quartus® Prime Pro Edition software version 24.3.1, the clock generated from the Configuration Clock IP is not considered in the timing analysis. The inaccurate constraints in the altera_s10_configuration_clock.sdc file caused this. The above problem might cause the following failure symptoms: If the clock generated from the Configuration Clock IP is used as the reference clock to generate the F-Tile protocol IP's reconfiguration clock, you might encounter access failures to: Avalon® Memory-Mapped (AVMM) interface Transceiver Tool Kit (TTK) Ethernet Tool Kit (ETK) If your design instantiated any IP encapsulating the Configuration Clock IP, you might get a similar warning message: CLK-30028 – Invalid Generated Clock – complaining master clock for these clock assignments could not be derived. For example, the following IPs have instantiated the Configuration Clock IP: F-Tile Avalon® Streaming IP for PCI Express R-Tile Avalon® Streaming IP for PCI Express Partial Reconfiguration Controller IP If the clock generated from the Configuration Clock IP is used to drive any modules, all the logic under this clock domain might behave abnormally. For example, you might encounter issues about: Hard Processor System (HPS) Lightweight HPS-to-FPGA (LWH2F) Resolution To work around the above problem, you can perform the following steps: Open the altera_s10_configuration_clock.sd c file. Change " create_clock -name altera_int_osc_clk -period 4.000 [get_nodes {*|intosc|oscillator_dut~oscillator_clock.reg}] " to " create_clock -name altera_int_osc_clk -period 4.000 [get_nodes {*|intosc|oscillator_dut~oscillator_clock}] ". Save the SDC file and recompile the design. A patch is available to fix this problem for the Quartus® Prime Pro Edition Software version 24.3.1 . Download and install patch 1.14 from the following links: Patch 1.14 for Windows* ( quartus-24.3.1-1.14-windows.exe ) Patch 1.14 for Linux* ( quartus-24.3.1-1.14-linux.run ) Readme for patch 1.14 ( quartus-24.3.1-1.14-readme.txt ) This problem has been fixed in the Quartus® Prime Pro Edition Software version 25.1. Custom Fields values: ['novalue'] Troubleshooting 15017209721 False ['Configuration Clock Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 25.1 24.3.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']