How can the PHYLite IP RZQ pin location be assigned? - How can the PHYLite IP RZQ pin location be assigned? Description The PHYLite IP does not have an RZQ input pin, which you can place directly. During compilation, the Quartus® Prime Software creates the ALTOCT IP functionality, including the RZQ signal, and defines its pin location. Resolution The RZQ signal can be assigned to a pin location using this flow : Under the PHYLite IP Group tab of the IP Parameter Editor, set the Group <number> OCT Settings section to your required OCT values. Generate and instantiate the IP in your project (or create the PHYLite example design project). Compile the project. The Quartus® Prime Fitter places the RZQ pin at a location it chooses, and if you look in the Fitter Report > Plan Stage > Input Pins, you will see an RZQ signal name similar to the following : <PHYLite_design_hierarchy>|core|arch_inst|u_phylite_io_bufs|data_io_buf_gen_grp[0].data_io_obuf_gen[0].u_data_buf~oct_cal_blockrzq_pad~bp A reason for running this initial compilation is to verify that the PHYLite IP can be placed successfully. To place the RZQ pin at your chosen RZQ-capable pin location, QSF assignments must be added to force the Quartus® Prime Fitter to place it in the desired location. In the Pin Planner, you can view the available RZQ pin locations in the Tasks window, OCT Pins > RZQ . Double-click on RZQ, and it displays the RZQ pins with a bold outline in the pin grid diagram. The example assignments shown here use the SSTL-15 I/O standard for the PHYLITE data and strobe pins. set_location_assignment PIN_AH3 -to octrzq set_instance_assignment -name IO_STANDARD "1.5 V" -to octrzq set_instance_assignment -name RZQ_GROUP OCTRZQ -to <io_strobe> set_instance_assignment -name RZQ_GROUP OCTRZQ -to <io_signal> Notes : a) Add the RZQ_GROUP assignment for all the data and strobe pins in the PHYLite interface. b) The name of the RZQ pin (octrzq in this example) is just a character string name and can be changed. Recompile the project. Verify in the Pin Planner that the RZQ pin is placed correctly. Note that you can ignore the following anomalies, which may occur in the fitted project : a) In the Pin Planner, the octrzq pin is placed at the chosen location, but it has a "?" shown in the node name pin list. b) In the Fitter report > Plan Stage > Input Pins , the RZQ pin is still named as <PHYLite_design_hierarchy>|core|arch_inst|u_phylite_io_bufs|data_io_buf_gen_grp[0].data_io_obuf_gen[0].u_data_buf~oct_cal_blockrzq_pad~bp Custom Fields values: ['novalue'] Troubleshooting FB: 519923; False ['PHY Lite for Parallel Interfaces Arria® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.0 17.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']