Why do the Hard IP for PCI Express user guides v13.1 and earlier state that the hip_reconfig_clk should not exceed 70Mhz? - Why do the Hard IP for PCI Express user guides v13.1 and earlier state that the hip_reconfig_clk should not exceed 70Mhz? Description The Altera® Hard IP for PCI Express® User Guides for Arria® V GZ, Arria 10, and Stratix® V devices previously had incorrect information. The correct frequency for the hip_reconfig_clk can be in the range of 50-125 MHz, there is no 70 MHz limitation. This information has been updated in the 14.0 version of the user guides. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 14.0 novalue ['Arria® 10 FPGAs and SoCs', 'Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']