Why aren’t the tx_polinv and rx_polinv ports available when using the transceiver Native PHY IP for Intel® Arria® 10 and Intel® Cyclone®10 devices in Enhanced PCS mode? - Why aren’t the tx_polinv and rx_polinv ports available when using the transceiver Native PHY IP for Intel® Arria® 10 and Intel® Cyclone®10 devices in Enhanced PCS mode? Description The transceiver Native PHY Intel® Arria® 10 and Intel® Cyclone® 10 FPGA IP in Enhanced PCS mode does not have tx_polinv and rx_polinv ports. Resolution You can use the Gearbox Enable RX data polarity inversion and Enable TX data polarity inversion settings to implement static polarity inversion. You can implement dynamic polarity inversion by reconfiguring the PHY with different Gearbox Enable RX data polarity inversion and Enable TX data polarity inversion settings. Custom Fields values: ['novalue'] Troubleshooting 15007199522 False ['Transceiver Native PHY Arria® 10 Cyclone® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 18.1 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs'] ['novalue'] ['novalue'] ['novalue']