Why does the IP upgrade fail for Intel® Arria® 10 FPGA Native PHY Intel® FPGA IP with manual CTLE mode and DFE enabled? - Why does the IP upgrade fail for Intel® Arria® 10 FPGA Native PHY Intel® FPGA IP with manual CTLE mode and DFE enabled? Description Due to a problem with the Intel® Arria® 10 FPGA Native PHY Intel FPGA IP, the IP upgrade to the Intel® Quartus® Prime Software version 16.0 from previous software versions might fail if you set CTLE mode to "manual" and enable DFE for data rates < 4.5 Gbps. The valid DFE mode is "disabled" when CTLE mode = "manual". You might also observe IP upgrade failure if the Native PHY Intel FPGA IP has multiple reconfiguration profiles enabled and if any profile has a configuration with CTLE mode = "manual" and DFE enabled for data rates < 4.5 Gbps Resolution To fix this problem, follow these steps: Open the Native PHY Intel FPGA IP in the IP parameter editor. Load the configuration profile with CTLE mode = "manual" and DFE enabled for data rates < 4.5 Gbps. Set DFE mode to "disabled". Save and generate your IP. Custom Fields values: ['novalue'] Troubleshooting FB: 368078; HSD: 1408177479 False ['Transceiver Native PHY Arria® 10 Cyclone® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 16.0 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']