Nios® V Processors Hardware Integration - 20 Minutes This Online training provides a step-by-step guide on how to configure parameters in Nios® V processors with Quartus® Prime and Platform Designer for system design. As Altera® ’s next generation soft core processor based on the open-source RISC-V, Nios V processors provide different applications for custom instruction and microcontroller embedded design. Nios V processors are designed for Altera® FPGA devices with support in all Quartus® Prime Software Editions Course Objectives At course completion, you will be able to: Understand the architecture and applications for Nios V Processors. Create an embedded design using Platform Designer to configure and connect the IP for Nios V/m, Nios V/g and Nios V/c, as well as project integration in Quartus Prime Software. Configure parameters and instantiate Nios V/m, Nios V/g and Nios V/c IP in Platform Designer using Agilex™ 5 FPGAs. Skills Required: Knowledge on Altera's soft-processor design flows. If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com Reference Course Code: FPGA_ONVHW. FPGA_ONVHW. <p>Nios V Processors Hardware Integration</p>