Modelsim Compilation Error with Generated Verilog Output File in Cyclone V - Modelsim Compilation Error with Generated Verilog Output File in Cyclone V Description Compilation error when modelsim is compiled with the generated verilog (.vo) output file. The error message: #** Error: (vsim-10000) ipfs_vo/t_RT_471_1of1.vo(4614): Unresolved defparam reference to ’channels’ in ni0OO1.channels" is displayed. This issue affects the 12.1sp1 version in Cyclone V. Resolution Open the verilog (.vo) file and search for altera_xcvr_reset-control block. Convert all the parameter names under defparam to upper case (for example, channels - CHANNELS). This issue is fixed in 13.0. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['novalue'] novalue novalue ['Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']