Critical Warning (169244): Total number of single-ended output or bi-directional pins in bank have exceeded the recommended amount in a bank where dedicated LVDS, RSDS, or mini-LVDS outputs exists. - Critical Warning (169244): Total number of single-ended output or bi-directional pins in bank have exceeded the recommended amount in a bank where dedicated LVDS, RSDS, or mini-LVDS outputs exists. Description This warning will be generated for designs using Cyclone® V devices in the Quartus® II software version 13.0sp1 when using differential and single-ended I/O standards in the same I/O bank. However, this warning may also be generated by mistake for banks that only contain single-ended I/O pins. Resolution The warning can be ignored if there are no LVDS, RSDS, or mini-LVDS signals in banks containing only single-ended I/O standards. The critical warning is scheduled to be fixed in Quartus® II software version 14.1 so that it is only generated in valid cases. Custom Fields values: ['novalue'] Troubleshooting 2205822342 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 14.1 13.0.1 ['Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']