Error(18510): PIPE master channel < ovSOFTPCIE_TxP[x] > can't be placed at the HIP channel location < PIN_xxxx > due to timing requirement. - Error(18510): PIPE master channel < ovSOFTPCIE_TxP[x] > can't be placed at the HIP channel location < PIN_xxxx > due to timing requirement. Description You may see this error, when compiling the Intel® Stratix® 10 L-Tile/H-Tile Transceiver Native PHY in Gen3 PIPE* configurations targetting -2/-3 speed grade Intel® Stratix® 10 devices using the Intel® Stratix® 10 Hard IP for PCI* Express pin locations. Resolution To work around this problem, either change the transceiver locations to avoid those used by the Intel® Stratix® 10 Hard IP or change the device speed grade to -1. This error will be reported when using Intel® Quartus® Prime Pro edition versions 17.0, 17.1and 18.0 when targetting a -2 or -3 speed grade. This error has been fixed starting in Intel® Quartus® Prime Pro edition version 18.1. Custom Fields values: ['novalue'] Troubleshooting FB: 1408206073; False ['PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1 17.1 ['Stratix® 10 GX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 SX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']