F-Tile PCIe Root port - rx_st_hdr_o - F-Tile PCIe Root port - rx_st_hdr_o Hello, Reading the F-Tile Avalon Streaming IP for PCIExpress User Guide , UG-20331 2026.02.11. In X4 configuration, the 'rx_st_hrd_o(127:0)' signals is valid when 'rx_st_sop'=1 and rx_st_valid_o'=1, is is correct ? If Yes, it means that even for just a Memory Read Command Data the 'rx_st_data_o(127:0)' signals are valid as well, correct ? If yes this data has to be ignored ? If not, please provide detail explanation about the validity of the 'rx_st_hrd_o(127:0)'. Thanks for help. Serge Replies: Re: F-Tile PCIe Root port - rx_st_hdr_o Hi Serge93 Thank you for your confirmation. I’m glad to hear that your question has been addressed. I will transition this thread to community support. If you have a new question, feel free to open a new thread to get support from Altera experts. Thanks. Best Regards, Ven Replies: Re: F-Tile PCIe Root port - rx_st_hdr_o Thank you Ven. This addresses my question; Serge Replies: Re: F-Tile PCIe Root port - rx_st_hdr_o Hi Serge93 The signals rx_st_hdr_o[127:0] are valid when rx_st_sop_o=1 and rx_st_valid_o=1, as these conditions indicate the start of a valid TLP packet on the RX Avalon-ST interface. However, this does not imply that rx_st_data_o[127:0] is also valid. The F-Tile RX interface uses separate parallel buses for header and data. The validity of rx_st_data_o[127:0] is determined by the TLP type, specifically the Fmt field in the TLP header carried on rx_st_hdr_o: When Fmt[2:0] = 000 or 001, the TLP has no data payload (e.g., Memory Read, Completion without Data), and rx_st_data_o must be ignored. For a Memory Read (MRd) request, the TLP consists of a header only with no data payload. Please let me know if this addresses your questions. Thanks. Best Regards, Ven Replies: Re: F-Tile PCIe Root port - rx_st_hdr_o Hi Serge93 Thank you for reaching out. Allow me some time to look into your issue. I shall come back to you with findings. Thanks. Best Regards, Ven