Introduction to Memory Interfaces IP in Altera® FPGA Devices - Same Course in Japanese: Generation 10デバイスのメモリ・インタフェース導入編 Same Course in Simplified Chinese: 第10代器件内存接口IP介绍 45 Minutes This training is part 1 of 4. Altera® Stratix® 10, Arria® 10, and Cyclone® 10 devices introduce a brand new, higher performance architecture for implementing external memory interfaces, including DDR4 running at up to 2.666 Gbps on some devices. This first part of the training introduces the memory options available and describes how the architecture makes such performance possible. It also describes the unique features of the built-in hard memory controller needed to achieve such speeds. Course Objectives At course completion, you will be able to: Know the external memory interface (EMIF) options available in the latest Altera® FPGA devices Understand the new architectural features for implementing memory interfaces Learn about the features of the new Hard Memory Controller that make higher speed interfaces possible Skills Required Background in digital logic design Basic knowledge of memory interfaces Familiarity with the Altera® Quartus® software Familiarity with memory interfaces in Altera® FPGA devices from either of the listed prerequisite training classes If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OMEM1121. FPGA_OMEM1121. <p>Introduction to Memory Interfaces IP in Altera FPGA Devices</p>