Does Quartus 20.1 std support VHDL 2008 vector aggregation? - Does Quartus 20.1 std support VHDL 2008 vector aggregation? I have something like the following: signal_a(7 downto 0) <= (3 downto 0 => "0001", others => '1'); I got error: Error (10515): VHDL type mismatch error at ***.vhd(###): std_ulogic type does not match string literal Please comment Replies: Re: Does Quartus 20.1 std support VHDL 2008 vector aggregation? Thank you for acknowledging the solution provided. I'm glad to hear that your question has been addressed. Now, I will transition this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Thank you and have a great day! Best Regards, Richard Tan Replies: Re: Does Quartus 20.1 std support VHDL 2008 vector aggregation? I believe you are correct - Quartus Standard does not support aggregates for VHDL 2008 due to its limited language support. The following list is the closest I could find of VHDL 2008 features that Quartus Standard supports, prior to the release of Quartus Pro version: https://www.intel.com/content/www/us/en/programmable/quartushelp/16.0/index.htm#hdl/vhdl/vhdl_list_2008_vhdl_support.htm I have try to run below code (Fail in Standard but Pass in Pro): library ieee; use ieee.std_logic_1164.all; entity Example is port ( clk : in std_logic; reset : in std_logic; out_data : out std_logic_vector(7 downto 0) ); end entity Example; architecture Behavioral of Example is signal signal_a : std_logic_vector(7 downto 0) := (others => '1'); begin process (clk, reset) begin if reset = '1' then -- reset the signal to the initial value signal_a <= (3 downto 0 => "0001", others => '1'); elsif rising_edge(clk) then -- do some processing using the signal out_data <= signal_a; end if; end process; end architecture Behavioral; Best Regards, Richard Tan p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey.