When using the Low Latency 40- and 100-Gbps Ethernet MAC and PHY, is it possible that both the start of packet and end of packet signals assert in the same clock cycle? - When using the Low Latency 40- and 100-Gbps Ethernet MAC and PHY, is it possible that both the start of packet and end of packet signals assert in the same clock cycle? Description Yes, when fragmented or short frames are received, the Low Latency 40- and 100-Gbps Ethernet MAC and PHY Intel® FPGA IP may assert both start of packet ( l<n>_rx_startofpacket/dout_sop ) and end of packet ( l<n>_rx_endofpacket/dout_eop ) signals in the same clock cycle . Resolution N/A Custom Fields values: ['novalue'] Troubleshooting - False ['novalue'] ['novalue'] novalue novalue ['Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']