Why does the High Speed Reed Solomon FPGA IP Core generate an incorrect set of check symbols for my data? - Why does the High Speed Reed Solomon FPGA IP Core generate an incorrect set of check symbols for my data? Description Due to a problem with the RTL source generation of the High Speed Reed Solomon FPGA IP Core, if the ' Hyper-optimization ' parameter is set to ' High ' the IP will generate an incorrect set of check symbols for the incoming data payload. Resolution To work around this problem, set the ' Hyper-optimization ' parameter to ' Low '. Custom Fields values: ['novalue'] Troubleshooting FB: 2007757464 / 1408300138; False ['IP High-Speed Reed-Solomon Encoder/Decoder IP-RSCODEC-HS'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 18.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']