Introduction to Hybrid Memory Cubes with Altera FPGAs - 21 Minutes Hybrid Memory Cube, or HMC, is the next generation of high-speed external memory technology. Multiple DRAM layers are connected to a logic base layer to form a 3-D, high capacity, small footprint package. Instead of the parallel interface used in traditional DDR-type memory, HMC uses high-speed transceiver links, abstracting away the complexities of DRAM timing. In this training, you'll be introduced to Hybrid Memory Cube, its architecture, how it compares to DDR-type memory, and how it works with Altera® FPGA devices. Note that the HMC Controller IP is currently only supported for members of the Arria® 10 device family. Course Objectives At course completion, you will be able to: Understand what a Hybrid memory Cube (HMC) is and its architecture Recognize the advantages of HMC over traditional source synchronous Parallel memory (DDR, QDR, etc.) Skills Required Background in digital logic design Familiarity with the Quartus Prime software Familiarity with high-speed transceivers If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OHMC101. FPGA_OHMC101. <p>Introduction to Hybrid Memory Cubes with Altera FPGAs</p>