How do I insert an LVDS buffer between an Altera_PLL and ALTLVDS_RX or ALTLVDS_TX megafunction in external PLL mode for Cyclone® V, Arria® V, and Stratix® V devices? - How do I insert an LVDS buffer between an Altera_PLL and ALTLVDS_RX or ALTLVDS_TX megafunction in external PLL mode for Cyclone® V, Arria® V, and Stratix® V devices? Description An LVDS buffer is required to be inserted between an Altera_PLL and ALTLVDS_RX or ALTLVDS_TX mega function when used in external PLL mode for Cyclone® V, Arria® V, and Stratix® V devices when any of the following options are turned on: Enable dynamic reconfiguration of PLL Enable access to dynamic phase shift ports Enable physical output clock parameters Resolution Download this How-To document to learn how you can add an intermediate LVDS buffer between the external PLL and ALTLVDS IP. The How-To document references example designs which you can download in VHDL or Verilog for each of the Cyclone® V, Arria® V, and Stratix® V devices: top-rxtx-external-pll-cyclonev-vhdl.zip top-rxtx-external-pll-cyclonev-verilog.zip top-rxtx-external-pll-arriav-vhdl.zip top-rxtx-external-pll-arriav-verilog.zip top-rxtx-external-pll-stratixv-vhdl.zip top-rxtx-external-pll-stratixv-verilog.zip Related Articles Error: SERDES DPA Block node 'lvds_rx:lvds_rx_inst0|altlvds_rx:ALTLVDS_RX_component|lvds_rx_lvds_rx:auto_generated|lvds_rx_dpa3' is not properly connected on the 'RXFCLK' port. It must be connected to one of the valid ports listed below. Info: Can be connected to LVDSCLK port of arriav_pll_lvds_output WYSIWYG Info: Can be connected to OUTCLK port of generic_pll WYSIWYG Error: SERDES DPA Block node 'lvds_tx:lvds_tx_inst0|altlvds_tx:ALTLVDS_TX_component|lvds_tx_lvds_tx:auto_generated|arriav_serdes_dpa1' is not properly connected on the 'TXFCLK' port. It must be connected to one of the valid ports listed below. Info: Can be connected to LVDSCLK port of arriav_pll_lvds_output WYSIWYG Info: Can be connected to OUTCLK port of generic_pll WYSIWYG Error: IR FIFO USERDES Block node 'lvds_rx:lvds_rx_inst0|altlvds_rx:ALTLVDS_RX_component|lvds_rx_lvds_rx:auto_generated|sd2' is not properly connected on the 'WRITECLK' port. It must be connected to one of the valid ports listed below. Info: Can be connected to LOADEN port of arriav_pll_lvds_output WYSIWYG Info: Can be connected to OUTCLK port of generic_pll WYSIWYG Info: Can be connected to LVDSCLK port of cyclonev_pll_lvds_output WYSIWYG Info: Can be connected to OUTCLK port of arriav_clkena WYSIWYG Error: IR FIFO USERDES Block node 'lvds_tx:lvds_tx_inst0|altlvds_tx:ALTLVDS_TX_component|lvds_tx_lvds_tx:auto_generated|lvds_outclk_tx_serialiser' is not properly connected on the 'LOADEN' port. It must be connected to one of the valid ports listed below. Info: Can be connected to LOADEN port of arriav_pll_lvds_output WYSIWYG Info: Can be connected to LOADEN port of cyclonev_pll_lvds_output WYSIWYG Info: Can be connected to OUTCLK port of generic_pll WYSIWYG Info: Can be connected to OUTCLK port of arriav_clkena WYSIWYG Error: SERDES receiver node 'lvds_rx:lvds_rx_inst0|altlvds_rx:ALTLVDS_RX_component|lvds_rx_lvds_rx:auto_generated|rx_0' is not properly connected on the 'CLOCK0' port. It must be connected to one of the valid ports listed below. Info: Can be connected to LVDSCLK port of stratixv_pll_lvds_output WYSIWYG Info: Can be connected to OUTCLK port of generic_pll WYSIWYG Error: SERDES transmitter node 'lvds_tx:lvds_tx_inst0|altlvds_tx:ALTLVDS_TX_component|lvds_tx_lvds_tx:auto_generated|outclock_tx' is not properly connected on the 'ENABLE0' port. It must be connected to one of the valid ports listed below. Info: Can be connected to LOADEN port of stratixv_pll_lvds_output WYSIWYG Info: Can be connected to OUTCLK port of generic_pll WYSIWYG How do I implement and connect between an external Altera_PLL and an ALTLVDS_RX with Dynamic Phase Alignment (DPA) enabled? Error (10228): Verilog HDL error at lvds_rx_lvds_rx.v(49): module lvds_rx_accum cannot be declared more than once Custom Fields values: ['novalue'] Troubleshooting 22011131652 False ['PLL'] ['FPGA Dev Tools Quartus II Software'] novalue 12.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']