Why Low Latency Ethernet 10G MAC 10M/100M/1G/10G Example Design may fail timing on multiple channels? - Why Low Latency Ethernet 10G MAC 10M/100M/1G/10G Example Design may fail timing on multiple channels? Description The following variants of Intel® Low Latency Ethernet 10G MAC example design may fail timing when number of channel more than or equal to 7. 1. 10M/100M/1G/10G Ethernet 2. 10M/100M/1G/10G Ethernet with 1588 3. 1G/10G Ethernet 4. 1G/10G Ethernet with 1588 Resolution This issue has been fixed in Quartus® Prime software versions 17.0 and onwards. Custom Fields values: ['novalue'] Troubleshooting FB: 414238; False ['Low Latency Ethernet 10G MAC IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 17.0 16.1 ['Arria® V FPGAs and SoCs', 'Arria® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']