Why does the Synopsys VCS* simulator fail when simulating the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example? - Why does the Synopsys VCS* simulator fail when simulating the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.2 and 23.3, Synopsys VCS* simulator fails when targeting the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example. Resolution To work around this problem, append the simulation switch " -debug_region=encrypt " in USER_DEFINED_ELAB_OPTIONS in the generated Synopsys VCS* simulation script (run_vcs.sh) for the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example. This problem is fixed in version 23.4 of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 16021082992 False ['Triple-Speed Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.4 23.2 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['Agilex™ 7 FPGA I-Series Dev Kit']