Why can't I place a reference clock for transceivers on the GXB_RX / GXB_REFCLK input? - Why can't I place a reference clock for transceivers on the GXB_RX / GXB_REFCLK input? Description Stratix® V, Arria® V, and Cyclone® V devices support placing an incoming dedicated transceiver reference clock on dual-use GXB_RX / GXB_REFCLK input pins. However, this functionality was not enabled until Quartus® II software version 12.1. Prior to Quartus II v12.1 reference clocks could only be placed on the dedicated REFCLK input pins. Resolution This functionality has been fully implemented as of Quartus II v12.1. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.1 novalue ['Arria® V FPGAs and SoCs', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V SX FPGA', 'Cyclone® V FPGAs and SoCs', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V FPGAs', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']