Why does the VIP suite CVO II IP have no output when video in and out use the same clock? - Why does the VIP suite CVO II IP have no output when video in and out use the same clock? Description Due to a problem with Clocked Video Output (CVO) II IP in Quartus® Prime software version v16.0, the CVO II IP may not generate output if the " Number of pixels in Parallel " has a value larger than 1 and the " Video in and out use the same clock " option is enabled. Resolution You can disable the " Video in and out use the same clock " option and manually connect the source clock to is_clk and vid_clk ports. This problem is fixed starting in Quartus Prime software version 16.1. Custom Fields values: ['novalue'] Troubleshooting FB: 380357; True ['Clocked Video Output II (4K Ready) IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 16.1 16.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']