VHDL Basic Course - 3 Days - Enroll Now This three-day class is a general introduction to the VHDL language and its use in programmable logic design. The emphasis is on the synthesis constructs of VHDL. You will gain a basic understanding of VHDL, enabling you to create your own designs. In the hands-on laboratory sessions, you will put this knowledge to the test by writing simple but practi-cal code. You will also learn the basic instructions needed for operating the synthesis and simulation tools Quartus®Prime Software. Furthermore the implementati-on of test benches and the use of ModelSim/Questa for VHDL simulation will be covered. Course Content: Modules 1. Basic VHDL (1 day) 2. Simulation with Questa (3/4 day) 3. Design Rules (1/4 day) 4. Advanced VHDL (1 day) Topics • Understanding the origin of the VHDL language • Understanding the language basics • Using VHDL building blocks (Design Units) o Entity o Architecture o Configurations o Package declarations o Package bodies • Ability to model code styles o Behavioral code style o Structural code style • Understanding the design methodologies of o VHDL and the differences in Synthesis models • Using VHDL for simulation • Working with ModelSim/Questa to perform both functional and gate level simulations Prerequisites: - Background in digital logic design - Prior, basic knowledge of a programming language or hardware description language is a plus - No prior knowledge of VHDL, Quartus Prime Software or ModelSim software is needed. Tools Required: - 17 inch Laptops for practical exercises will be provided - You can also bring your own computer with the following tools installed o Quartus Prime Lite Edition, V 24.1 o Questa – Altera FPGA Starter Edition Software. ELCA_VHDL.