Why does Agilex® 7 FPGA M-Series fail to launch U-Boot proper after a Warm reset in release 25.3.1 and later? - Why does Agilex® 7 FPGA M-Series fail to launch U-Boot proper after a Warm reset in release 25.3.1 and later? Description Due to corruption in the device tree on the Warm reset flow in the Agilex® 7 FPGA M-Series device, the resolution of the u-boot,spl-boot-order = &mmc node fails at the re-entry of the U-Boot SPL, resulting in the loading of the U-Boot proper failing. The error observed is the following: Hit any key to stop autoboot: 0 SOCFPGA_AGILEX7M # reset -w resetting ... Do warm reset now... U-Boot SPL 2025.10 (Dec 11 2025 - 10:49:42 +0000) Reset state: Warm (Triggered by MPU 0) MPU 1350000 kHz L4 Main 400000 kHz L4 sys free 100000 kHz L4 MP 200000 kHz L4 SP 100000 kHz SDMMC 50000 kHz HBM: SDRAM init in progress ... HBM: Calibration success HBM: Warning: DRAM size from device tree (2048 MiB) mismatch with hardware (4096 MiB). HBM: 2048 MiB HBM: size check success HBM: firewall init success HBM init success board_boot_order: no valid element spl-boot-order list SPL: failed to boot from all boot devices ERROR ### Please RESET the board This problem is observed regardless of the method used to apply the Warm reset, and this is present in release 25.3.1 and later. Resolution There is no workaround for this problem. This will be fixed in a future release. Custom Fields values: Troubleshooting ES-14530 novalue ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.3.1 ['Agilex® 7 FPGAs and SoCs']