Why is the F-Tile HDMI Intel® FPGA IP Design Example with Fixed Rate Link (FRL) and Transition Minimized Differential Signaling (TMDS) mode on clocked video interface not working? - Why is the F-Tile HDMI Intel® FPGA IP Design Example with Fixed Rate Link (FRL) and Transition Minimized Differential Signaling (TMDS) mode on clocked video interface not working? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.4, changes to the SystemPLL IP caused the rx_tmds_clk to not toggle/stay low. Without this clock operating correctly, the Transition Minimized Differential Signaling (TMDS) mode will not work. Resolution A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition Software version 22.4. Download and install Patch 0.04 from the following links: Version 22.4 Patch 0.04 for Windows (.exe) Version 22.4 Patch 0.04 for Linux (.run) Readme for version 22.4 Patch 0.04 (.txt) This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15012451682 False ['HDMI'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.1 22.4 ['Agilex™ 7 FPGA F-Series'] ['novalue'] ['novalue'] ['novalue']