Is there any issue with selecting the option Enable Avalon-MM byte-enable signal when generating RLDRAMII Controller with UniPHY? - Is there any issue with selecting the option Enable Avalon-MM byte-enable signal when generating RLDRAMII Controller with UniPHY? Description Yes, the option "Enable Avalon-MM byte-enable signal" in the Controller Settings tab of the RLDRAMII Controller with UniPHY in version 11.0 does not have any effect on the controller. When enabled, no controller port for avl_be is created or used in any way. There is no workaround to implement byte enable. This issue will be fixed in the future version of the IP and Quartus ® II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']