Can the Intel® Stratix® 10 HBM2 efficiency monitor test pattern run in an infinite loop? - Can the Intel® Stratix® 10 HBM2 efficiency monitor test pattern run in an infinite loop? Description The efficiency monitor test pattern is implemented to run only one loop regardless of the traffic generator parameter setting. Resolution To make the test pattern run continuously, toggle the wmcrst_n_in signal after the traffic_gen_pass signal is asserted high. Custom Fields values: ['novalue'] Troubleshooting 1508184108 False ['External Memory Interfaces Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 19.1 ['Stratix® 10 MX FPGA'] ['novalue'] ['novalue'] ['novalue'] - 2023-05-23