Why do the F2H (FPGA2HPS) subordinate signals showing "zzzzz"? - Why do the F2H (FPGA2HPS) subordinate signals showing "zzzzz"? Description Due to a problem with the QuestaSim* SE on Quartus ® Prime Pro Edition Software version 25.1.1, when using the BFM testbench on F2H (FPGA2HPS) AXI4 and ACE-lite bridge, subordinate signals may appeared to have “zzz” or “ZZ” in the readings. Example of signal waveform in QuestaSim with “zzz” or “ZZ”: Impact: In QuestaSim, a "zzz" or "ZZ" signal usually indicates a high-impedance state (floating) or uninitialized value in the VHDL simulation, often appearing in the Wave window when signals are not being driven or have not received a value. Resolution Possible workarounds: Add Missing Pull-up/Pull-down resistors: If the signal is intended to be high or low when not driven, ensure a pull-up or pull-down resistor is properly modeled. Fix Unconnected Port: Ensure signal in the waveform is connected correctly in the testbench. Optimization Issues: Design optimization can cause signals to appear missing or in an incorrect state. Try adding +acc to the vsim command to improve visibility, e.g. vsim -voptargs=+acc <top_module> This problem is scheduled to be fixed in a future release of the Quartus ® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 14025107135 novalue ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.1.1 ['Agilex™ 7 FPGAs and SoCs'] ['Simulation Dev Tools Questa'] ['novalue'] ['novalue']