Why does the number of paths in the "Paths reported per clock domain" report not match the number of paths reported in Timing Analyzer? - Why does the number of paths in the "Paths reported per clock domain" report not match the number of paths reported in Timing Analyzer? Description Due to a problem in the Intel® Quartus® Prime Pro Edition software version 20.1, you may see the number of paths reported in the "Paths reported per clock domain" does not match the number of paths reported in the Timing Analyzer GUI, such as the reported number is 999 in the Assignment->Settings->Timing Analyzer->Report worst-case paths during compilation->Paths reported per clock domain, the path number reported by Compilation Report->Timing Analyzer GUI is 1000. Resolution This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition software version 20.3. Custom Fields values: ['novalue'] Troubleshooting 1507853445 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.3 20.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']