Why might an Arria V, Cyclone V or Stratix V device transceiver not work correctly when an fPLL is used as a Tx PLL as well as a general purpose PLL? - Why might an Arria V, Cyclone V or Stratix V device transceiver not work correctly when an fPLL is used as a Tx PLL as well as a general purpose PLL?
Description An Arria® V, Cyclone® V or Stratix® V device transceiver may not work correctly when an fPLL is used as a Tx PLL as well as a general purpose PLL if its VCO frequency is not correct. Resolution When using an fPLL as a Tx PLL, you should ensure that you choose a VCO frequency that supports the datarate entered into your Native PHY IP. Other general purpose clocks outputted by the fPLL should be based upon the same VCO frequency. The fPLL VCO frequency can be inspected in the Quartus® II Fitter report.
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Troubleshooting
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['Arria® V GT FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Stratix® V FPGAs', 'Stratix® V GS FPGA', 'Stratix® V GX FPGA']
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['novalue'] - 2021-08-25
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