Why is the port name xxx_I changed to xxx_I_<num> when generating a VQM file? - Why is the port name xxx_I changed to xxx_I_<num> when generating a VQM file? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.3 and earlier, you might see the design port xxx_I is changed to xxx_I_<num> when generating a VQM file. This problem occurs if your design contains two ports; one is xxx, and the other is xxx_I. Resolution This problem is scheduled to be resolved in a future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15014425992 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.1 22.4 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']