Why does the Arria® 10 HDMI FPGA IP Design Example polarity inversion setting not affect the generated RTL? - Why does the Arria® 10 HDMI FPGA IP Design Example polarity inversion setting not affect the generated RTL? Description Due to a problem in the Arria® 10 FPGA HDMI FPGA IP Design Example when using the Quartus® Prime Pro Edition Software version 23.4, the polarity inversion setting for the HDMI RX PHY does not affect the generated RTL. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition Software version 23.4. Download and install Patch 0.63 below. Step to enable polarity inversion: Apply patch Generate design example Edit ./rtl/ip/nios/intel_hdmi_rx_phy.ip in the IP GUI and set parameters based on user requirement regenerate the IP by clicking "generate HDL" Compile the design Run in the hardware This problem is fixed beginning with version 25.1 of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15016638462 False ['Interfaces Audio/Video HDMI (Primary)'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 25.1 23.4 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']