Why do I get a segment violation during the Plan stage? - Why do I get a segment violation during the Plan stage? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 18.1, you may see this error during the plan stage of compilation. This error will have the following stack trace: Segment Violation at <> Module: quartus_fit RTM_CONSTRAINT_GRAPH::is_relevant_ct(unsigned int, unsigned int) const (tsm_rtm) void RTM_MIN_COST_FLOW_RETIMER::init_flow_problem<lemon::NetworkSimplex<lemon::SmartDigraph, long, signed char>, true>(lemon::NetworkSimplex<lemon::SmartDigraph, long, signed char>&) (tsm_rtm) Resolution To work around this problem, either: Rerun the plan stage as this error occurs infrequently. Add this .qsf (Quartus Settings File) assignment to prevent the retimer from being run during the plan stage set_global_assignment -name FITTER_EARLY_RETIMING OFF This problem is scheduled to be fixed in a future release of the Intel Quartus Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting FB: 593337; False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1.1 18.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']