Why is readdatavalid not asserted in Intel Agilex® EMIF Intel® FPGA IP Memory-Mapped Configuration and Status Register (MMR) Interface? - Why is readdatavalid not asserted in Intel Agilex® EMIF Intel® FPGA IP Memory-Mapped Configuration and Status Register (MMR) Interface? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.2 and earlier, when Intel Agilex® EMIF Intel® FPGA IP Memory-Mapped Configuration and Status Register (MMR) Interface is enabled, you might see that read data is available but readdatavalid signal is not asserted in MMR interface. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3. Custom Fields values: ['novalue'] Troubleshooting 1509233936 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.3 21.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']