Verifying Memory Interfaces IP in Altera® FPGA Devices - Same Course in Simplified Chinese: 第10代器件内存接口IP验证 Same Course in Japanese: Generation 10デバイスにおけるメモリ・インタフェースIPの検証 31 Minutes This training is part 3 of 4. Altera® Stratix® 10, Arria® 10, and Cyclone® 10 devices introduce a brand new, higher performance architecture for implementing external memory interfaces, including DDR4 running at up to 2.666 Gbps on some devices. This part of the training discusses how to perform a simulation of the altera_emif IP either by itself or using the generated example design. When generated, the IP creates all the files needed to perform a simulation. Timing analysis of the IP is also discussed along with suggestions for timing closure. The hard resources used for altera_emif along with easier-to-read timing reports simplifies analysis and closure. Course Objectives At course completion, you will be able to: Verify the functionality of an Altera® FPGA EMIF design through simulation Perform a normal timing analysis or use the new early I/O timing analysis Skills Required Background in digital logic design Basic knowledge of memory interfaces Familiarity with the Altera® Quartus® Prime software Familiarity with memory interfaces in Altera® FPGA devices from the listed prerequisite training classes If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OMEM1123. FPGA_OMEM1123. <p>Verifying Memory Interfaces IP in Altera FPGA Devices</p>