Why does the Arria 10 ATX PLL pll_cal_busy signal assert even without ATX PLL calibration? - Why does the Arria 10 ATX PLL pll_cal_busy signal assert even without ATX PLL calibration? Description You may see the pll_cal_busy signal of the Intel® Arria® 10 ATX PLL assert when the internal configuration bus is returned to the PreSICE even though no ATX PLL calibration is requested. This is a known issue with the Intel® Arria® 10 PreSICE. Resolution If ATX PLL calibration is not required, write the value of 2'b00 to offset address 0x100[1:0] before the internal configuration bus is returned to the PreSICE. This has already been fixed in Intel® Quartus® Prime Pro Edition Software 17.0. Custom Fields values: ['novalue'] Troubleshooting FB: 433249; False ['PLL Reconfig IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 17.0 16.1.2 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']