Why does Timing Analyzer report negative-edge clocks as positive-edge clocks? - Why does Timing Analyzer report negative-edge clocks as positive-edge clocks? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2 and earlier, you may see negative-edge clocks being reported as positive-edge clocks by Timing Analyzer for registers in IO Cells. This problem only affects designs targetting Intel Agilex® devices. Resolution To work around this problem, manually disable register packing on any FF that has an inverted clock in an IO Cell. For example: set_instance_assignment -name FAST_INPUT_REGISTER -to <to> -entity <entity name> OFF set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER -to <to> -entity <entity name> OFF set_instance_assignment -name FAST_OUTPUT_REGISTER -to <to> -entity <entity name> OFF This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition software version 22.3. Custom Fields values: ['novalue'] Troubleshooting 14017165872 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.3 21.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']