IPM-LDPC - For design that uses shorter packets and codes, a subset of our prevalidated and improved IPM-LDPC is available to protect your private datas. IP-Maker was founded in 2010 by high throughput bus experts. IP-Maker is a young and dynamic team of senior electronic engineers who will help your company leverage on the latest technological… Arria® 10 GT FPGA Arria® 10 GX FPGA IP-Maker's powerful IPM-LDPC is based on the LDPC algorithm. The IP-Maker IPM-LDPC Encoder/Decoder is full-featured with multiple parameters to fit your own needs in FPGA and SoC designs. In fact IPM-LDPC Encoder/Decoder is fully configurable, allowing to it reach the best latency or the smallest footprint. Customizable parameters include: number of check per bit, number per iteration, block size, bit error rate. Aerospace Consumer IPM-LDPC Key Features Adaptable BER Offering Brief No No No No Verilog Arria® 10 GT FPGA Arria® 10 GX FPGA No Yes 24.1.1 Offering Brief Development a1JUi000004YJabMAG What's Included IP core in source code or in netlist Ordering Information IPM-LDPC Direct a1JUi000004YJabMAG Development Intellectual Property (IP) a1MUi00000BOWp7MAH a1MUi00000BOWp7MAH Member 2026-06-16T23:52:42.000+0000 For design that uses shorter packets and codes, a subset of our prevalidated and improved IPM-LDPC is available to protect your private datas. Partner Solutions