Why does Qsys fail to generate any HDL files? - Why does Qsys fail to generate any HDL files? Description Qsys will fail to generate any HDL files if a Qsys component has a name that is illegal in either VHDL or Verilog HDL. For example in VHDL a name that ends in an underscore is illegal. Resolution To avoid this problem, ensure all your component names are legal. In a future release of the Quartus ® II software, Qsys is scheduled to produce an error message in this situation. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']