Agilex 7 Compile Internal Error - Agilex 7 Compile Internal Error I am getting an internal error during fitter in Quartus 24.1: Sub-system: PHYCLK, File: /quartus/periph/phyclk/phyclk_gen7.cpp, Line: 1590. I've attached the full error message, as well as an archive of a simplified project that creates the error. The error seems to be related to having multiple instances of the LVDS SERDES IP. The design has 4 instances of the IP block created in the design through a generate for loop. If I modify the loop to be 0..0 instead of 0..3 then compilation completes with no errors. Replies: Re: Agilex 7 Compile Internal Error Hi, Check this kdb link https://www.intel.com/content/www/us/en/support/programmable/articles/000099084.html for 24.1 patch. This internal error had been fixed in 24.2 and onwards. Thanks, Regards, Sheng Replies: Re: Agilex 7 Compile Internal Error Hi, I had reported the problem and will get back to you once any further feedback. Replies: Re: Agilex 7 Compile Internal Error Hi, Let me check with window version and get back to you Thanks, Regards, Sheng Replies: Re: Agilex 7 Compile Internal Error Thanks for the update. No luck with cleaning the project, I am still getting the internal error. I setup a virtual machine with Linux and 24.1 and it compiled fine, so looks like it might be an issue with Windows version. I assume you used Linux? I also tried recompiling with different number of instances of the LVDS block by modifying the generate loop. 0..0, 0..1, 0..2 and 1..3 all compile with no issue, but 0..3 gives me the internal error. Replies: Re: Agilex 7 Compile Internal Error Hi, I try to compile without error. May be try to Project -> Clean Project then recompile again. Attached the compiled design with database for your reference. Thanks, Regards, Sheng