Why do I see the fitter error "Can't place multiple pins assigned to pin location PIN" for AVSTx8 data signal? - Why do I see the fitter error "Can't place multiple pins assigned to pin location PIN" for AVSTx8 data signal? Description Due to Avalon-ST x8 mode uses the SDM_IO bank, which is dedicated IO for configuration signal, AVSTx8 cannot place to userI/O pins. In Intel Stratix10® pin connection guide page7, table3. Avalon-ST x8 mode uses the SDM_IO pins. SDM IO bank is dedicated IO for configuration signal, cannot locate user I/O. https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/dp/stratix-10/pcg-01020.pdf In Stratix10 Configuraition User Guide page12, table4, it said AVSTx8 signals are dedicated, cannot use dual purpose user IO. https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/stratix-10/ug-s10-config.pdf Only dual purpose configuration pins can user as user I/O during user mode. It describes in note15. AVST_DATA, AVST_VALID, and AVST_CLK. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue novalue ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']