Generation 10 Transceiver Clocking - 28 Minutes In the Generation 10 Transceiver Clocking course, you will learn the architecture of the clocking resources found in Altera® Arria® 10 high-speed transceivers. By learning this architecture, you will be able to maximize your transceiver channel usage, possibly leading to a cost reduction by using a smaller FPGA with lesser transceiver channels. You will also be able to avoid transceiver design issues by applying an understanding of transceiver clocking structure. Course Objectives At course completion, you will be able to: Describe the Arria® 10 transceiver clocking structure Select a successful transceiver layout based on the clocking resources available Avoid compilation errors by making valid clock connections Skills Required Familiarity with FPGA/CPLD design flow Familiarity with FPGA architecture Knowledge of Arria® 10 transceiver architecture Familiarity with high-speed interfaces and transmission protocols is helpful, but not required If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OG10XCVRCLK. FPGA_OG10XCVRCLK. <p>Generation 10 Transceiver Clocking</p>