Why does the HPS SDRAM fail to calibrate on my single-core SOC FPGA? - Why does the HPS SDRAM fail to calibrate on my single-core SOC FPGA? Description Due to a problem in the Quartus® II software version 13.1 and 14.0, the DDR IO settings in the software handoff files for single-core SOC FPGAs may be incorrect leading to SDRAM calibration failures on the HPS SDRAM controller. Resolution To work around this problem follow the steps below: Make a copy of your Quartus II and Qsys Project and target the dual-core variant of the SOC FPGA you are using Compile your dual-core Quartus II project Create a new BSP based on the dual-core Quartus II project using bsp-editor, but do not run make Copy the following file from the duel-core Preloader BSP into the single-core BSP Preloader spl_<bsp name>/generated/Iocsr_config_cyclone5.c Clean and make your single-core Preloader: make clean make Optional : Check that <Single-core BSP>/uboot-socfpga/board/altera/socfpga/iocsr_config_cyclone5.h matches the iocsr_config_cyclone5.h file in your dual-core preloader BSP This problem is scheduled to be resolved in a future release of the Quartus II Software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 13.1 ['Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']