Internal Error: Sub-system: U2B2_CDB, File: /quartus/db/u2b2/u2b2_nd_io48tile_config_creator_module.cpp, Line: 12265 - Internal Error: Sub-system: U2B2_CDB, File: /quartus/db/u2b2/u2b2_nd_io48tile_config_creator_module.cpp, Line: 12265 Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2 or earlier, you might see this internal error when compiling a design targeting the Intel® Stratix® 10 device family. The error occurs in designs containing an IOPLL Intel® FPGA IP where the refclk is assigned the LVDS I/O standard and the extclk_out port(s) are assigned the Differential 1.2-V SSTL I/O standard. Resolution To avoid this error, change the I/O standard of the extclk_out port(s) to LVDS as Differential 1.2-V SSTL is an unsupported I/O standard for the extclk_out port(s). Custom Fields values: ['novalue'] Troubleshooting 18023023278 False ['IOPLL IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 22.2 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']