How do I implement and connect between an external Altera_PLL and an ALTLVDS_RX with Dynamic Phase Alignment (DPA) enabled? - How do I implement and connect between an external Altera_PLL and an ALTLVDS_RX with Dynamic Phase Alignment (DPA) enabled? Description When using ALTLVDS_RX in external PLL mode with DPA enabled in Quartus® II software versions 12.1 and later, you will receive an error in Analysis and Synthesis as shown below: Error: SERDES DPA Block node \'lvds_rx:lvds_rx_inst0|altlvds_rx:ALTLVDS_RX_component|lvds_rx_lvds_rx:auto_generated|lvds_rx_dpa3\' is not properly connected on the \'DPACLKIN\' port. It must be connected to one of the valid ports listed below. Info: Can be connected to PHOUT port of arriav_pll_dpa_output WYSIWYG Info: Can be connected to OUTCLK port of generic_pll WYSIWYG This affects Arria® V and Stratix® V devices. Resolution Modify your design when using the ALTLVDS_RX megafunction in external PLL mode with DPA enabled by downloading this How-to document and example-project.zip file. First, you will need to complete the steps for implementing ALTLVDS_RX and ALTLVDS_TX with external PLL mode as described in the related solution below. Related Articles How do I insert an LVDS buffer between an Altera_PLL and ALTLVDS_RX or ALTLVDS_TX megafunction in external PLL mode for Cyclone V, Arria V, and Stratix V devices? Error (10228): Verilog HDL error at lvds_rx_lvds_rx.v(49): module lvds_rx_accum cannot be declared more than once Custom Fields values: ['novalue'] Troubleshooting 22011131652 False ['ALTLVDS_RX'] ['FPGA Dev Tools Quartus II Software'] No plan to fix 12.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']