Why do I see receiver error and replay timer timeout from my design with the F-Tile Avalon® Streaming FPGA IP for PCI Express* on hardware? - Why do I see receiver error and replay timer timeout from my design with the F-Tile Avalon® Streaming FPGA IP for PCI Express* on hardware? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.2, when you perform link disable, hot reset, equalization redo, or speed change (at Gen 4 and Gen 3), there is a chance of running into receiver error. Replay timer timeout may be observed when performing L0 and L1 link state changes by means of power management. Resolution Receiver error and replay timer timeout are correctable errors allowed by PCI Express® specifications. The occurrence is limited during the link operations as described above. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 23.4.1. Custom Fields values: ['novalue'] Troubleshooting 15013923823 False ['F-Tile Avalon-ST for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.4 23.2 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']