D16950 - Expanded UART with FIFO, hard and soft flow control, synchronous mode - Expanded UART with FIFO, hard and soft flow control, synchronous mode Based in Poland, European Union, our company provides Verilog and VHDL high quality synthesizable IP Cores of processors and microcontrollers, bus interfaces, arithmetic coprocessors and components… Arria® 10 SX FPGA Cyclone® III FPGA Cyclone® IV GX FPGA Agilex™ 5 FPGA E-Series MAX® 10 FPGA Cyclone® V SX FPGA Arria® V GZ FPGA Agilex™ 9 FPGA Direct RF-Series MAX® V CPLD Agilex™ 7 FPGA I-Series Arria® V SX FPGA Stratix® 10 DX FPGA Stratix® 10 SX FPGA Agilex™ 7 FPGA M-Series Cyclone® V GT FPGA Arria® 10 GT FPGA Arria® V ST FPGA Arria® 10 GX FPGA Stratix® 10 TX FPGA Cyclone® V SE FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Arria® V GX FPGA Cyclone® V E FPGA Agilex™ 3 FPGA C-Series Cyclone® V GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Cyclone® V ST FPGA Agilex™ 5 FPGA D-Series Stratix® 10 GX FPGA Arria® V GT FPGA Cyclone® 10 LP FPGA Agilex™ 7 FPGA F-Series Cyclone® 10 GX FPGA Stratix® 10 AX FPGA Cyclone® IV E FPGA Stratix® III FPGA Soft core of a Universal Synchronous and Asynchronous Receiver/Transmitter (UART), functionally compatible to the OX16C950. Allows serial transmission in two modes: UART and FIFO. In the FIFO mode, internal FIFOs are activated allowing 128 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit modes. Our efficient Core performs serial-to-parallel conversion on data characters received from a peripheral device or MODEM, but also parallel-to-serial conversion on data characters received from the CPU. The processor can read the complete status of the UART at any time during the functional operation. The reported status information includes the type and condition of transfer operations performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt). The D16950 includes a programmable baud rate generator which is able to divide a timing reference clock input by divisors of 1 to (216-1) and produce an n × clock for driving internal transmitter logic. Provisions are also included to use this n × clock to drive receiver logic. We also equipped our core with complete MODEM-control capability and a processor-interrupt system. Interrupts can be programmed according to your requirements, minimizing the computing required to handle the communications link. The D16950 core includes all (16450, 16550, 16650 and 16750) features and additional functions. Access Aerospace Consumer Defense Government Industrial Medical Transportation D16950 - Expanded UART with FIFO, hard and soft flow control, synchronous mode Key Features Software compatible with 16450, 16550,16650,16750 and 16950 UARTs Offering Brief No No No Yes Encrypted Verilog Verilog Arria® 10 SX FPGA Cyclone® III FPGA Cyclone® IV GX FPGA Agilex™ 5 FPGA E-Series MAX® 10 FPGA Cyclone® V SX FPGA Arria® V GZ FPGA Agilex™ 9 FPGA Direct RF-Series MAX® V CPLD Agilex™ 7 FPGA I-Series Arria® V SX FPGA Stratix® 10 DX FPGA Stratix® 10 SX FPGA Agilex™ 7 FPGA M-Series Cyclone® V GT FPGA Arria® 10 GT FPGA Arria® V ST FPGA Arria® 10 GX FPGA Stratix® 10 TX FPGA Cyclone® V SE FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Arria® V GX FPGA Cyclone® V E FPGA Agilex™ 3 FPGA C-Series Cyclone® V GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Cyclone® V ST FPGA Agilex™ 5 FPGA D-Series Stratix® 10 GX FPGA Arria® V GT FPGA Cyclone® 10 LP FPGA Agilex™ 7 FPGA F-Series Cyclone® 10 GX FPGA Stratix® 10 AX FPGA Cyclone® IV E FPGA Stratix® III FPGA Yes Yes 25.1.1 Offering Brief Production a1JUi0000049UApMAM What's Included HDL Source Code Ordering Information D16950 a1JUi0000049UApMAM Production Intellectual Property (IP) a1MUi00000BO8rgMAD a1MUi00000BO8rgMAD Select 2026-04-21T12:58:30.000+0000 Expanded UART with FIFO, hard and soft flow control, synchronous mode Partner Solutions